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POWER OPTIMIZATION TECHNIQUES FOR SEQUENTIAL ELEMENTS USING PULSE TRIGGERED FLIP-FLOPS

ABSTRACT

                    Flip-flops are the major storage elements in all SOC’s of digital design. They accommodate most of the power that has been applied to the chip. Flip-flop is one of the most power consumption components. It is important to reduce the power dissipation in both clock distribution networks and flip-flops. The power delay is mainly due to the clock delays. The delay of the flip-flops should be minimized for efficient implementation. The concept of this paper is to reduce the power consumption and to increase the speed and functionality of the chip. This paper moves around in replacing conventional master-slave based flip flop to a pulse triggered flip flop which act as a tribute alternate for low power applications. Initially in the critical path the pulse generation control logic along with AND function is removed to enhance faster discharge. A simple two-transistor AND gate design is used to reduce the circuit complexity. To increase further discharging speed conditional pulse enhancement scheme is introduce. In this scheme transistor sizes and pulse generation circuit can be further reduce for power saving. Here UMC CMOS 90nm technology is use in SPICE tool to design the proposed structure. This would bring up the result in power saving approximately to 38.4%.

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About the Author

Dr.M.ANTO BENNET

 Professor,Department of ECE, VELTECH, Chennai-600062

email: bennetmab@gmail.com

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